1. Technical Field of the Invention
The present invention relates to a multilevel wiring structure used in semiconductor devices, in which wires are formed of either copper or a material containing copper as a principle component, and to a method of fabricating such a structure.
2. Art Background
With the improvement in integration in semiconductor devices, problems such as an increase in wiring delay, deterioration in reliability of the wiring, and so on occur. As a method of solving the problems, copper wiring lines having a resistivity which is lower than that of conventional aluminum (Al) alloy wiring lines are being actively developed. In the context of integrated circuit devices, the wiring lines are formed by defining grooves or trenches in a substrate and filling those grooves or trenches with conductive material. For convenience, wiring lines are hereinafter referred to as wires. Copper wires, however, oxidize easily and the oxidized copper has inferior electrical properties to unoxidized copper. Therefore, it is difficult to fabricate a multilevel structure due to the copper oxidation that occurs during the process.
Copper also diffuses quickly in silicon (Si) and oxidized Si (SiO.sub.2). When copper diffuses into an insulating film such as SiO.sub.2, there is a possibility of deterioration in the device characteristics such as an increase in leakage current between wires, an increase in a leakage current at junctions, and the like. To avoid this problem, the multilevel metal structure shown in FIG. 1 was proposed. According to the conventional multilevel structure, tantalum (Ta) or the like is sandwiched as a barrier metal 10, which prevents the diffusion of copper, between the copper 60 and the SiO.sub.2 film 20. According to this structure, a boron implantation layer 30 which acts to suppress oxidation of copper is applied over the surface of a wiring 40 of the first layer. The first level of wire 40 and the second level of wire 50 are electrically connected by via plugs 60, each surrounded by a barrier metal 10.
The multilevel wiring structure depicted in FIG. 1 is fabricated by immersing the substrate into a dilute hydrofluoric acid solution as a pretreatment for forming the via plug. The copper surface is thereby subjected to a cleaning treatment in the dilute hydrofluoric acid solution, obtained by mixing 1 part by volume of hydrofluoric acid with 50 parts by volume of pure water, just before the barrier Ta is deposited. Typically, the diameter of a via hole is equal to 0.3 microns or less in the device depicted in FIG. 1.
The contact resistivity at the via connecting portion of the structure depicted in FIG. 1 is 1.5.times.10.sup.-8 .OMEGA.-cm.sup.2. When the contact resistance of a via connection having a diameter of 0.3 .mu.m is calculated from the above contact resistivity, a large value of 21 .OMEGA. is obtained so that an increased wiring delay occurs. In order to suppress this increase in the wiring delay, it is necessary to set the resistivity per via hole to approximately 2 .OMEGA. or less, which corresponds to 1/10 of the conventional value.